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MPC7400/10 implementation

This course covers NXP G4 Power CPUs

Objectives

  • The course provides coding guidelines based on the knowledge of the instruction pipeline.
  • Data flows between SDRAM, L1 caches and L2 cache are highlighted.
  • Cache coherency protocol is introduced in increasing depth.
  • Vector instructions and new C operators are viewed in detail.
  • Data streams parameterizing is emphasized through an example.
  • This course covers bus operation, either 60X or MPX mode.
  • Through a FFT algorithm, the instructor shows how to vectorize processing and reduce execution time using data streaming.
  • The internal performance monitor has been programmed so that different versions of the FFT algorithm implementation can be compared.
A more detailed course description is available on request at training@ac6-training.com
  • Experience of a 32 bit processor or DSP is mandatory.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • Superscalar out-of-order execution
  • Branch Target Instruction Cache
  • Static vs dynamic branch prediction
  • Coding guidelines
  • Cache basics
  • PLRU L1 replacement algorithm, FIFO L2 replacement algorithm
  • Hardware data cache flush
  • Cache coherency based on snooping, the MEI, MESI and MERSI state machines
  • Data and instructions queuing mechanism to decouple bus operation and internal activity
  • The Memory Sub System
  • The load fold queue and the store miss merging
  • Power management
  • Performance monitor
  • JTAG debugger
  • Differences between 7400 and 7410
  • User registers
  • Branch instructions
  • Integer instructions
  • IEEE754 floating point standard
  • Float instructions
  • EABI introduction
  • Cache related instructions
  • Little-endian emulation
  • PowerPC timers
  • Altivec registers
  • Vector load / store instructions
  • Vector integer instructions
  • Vector float instructions
  • Vector permut instructions
  • ANSI C extensions to support vectors
  • Altivec implementation on 7400/10
  • Data streams
  • MMU goals
  • Process protection
  • Tablesearch, hash value
  • MMU implementation in real-time sensitive applications
  • Supervisor registers
  • Context saving through SRR0/SRR1 registers
  • Handler table
  • Exception nesting
  • Auto-check on power up
  • Bus features : address pipelining, split transactions
  • 60X bus cycles
  • MPX data only transactions
  • Synchronous SRAM technologies
  • L2 bus interface
Duration
5 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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