STR2 | STR750F implementation |
This course covers STR750 ARM-based MCU family
Objectives
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- This course provides an overview of the ARM7TDMI core. Our course reference R1 - ARM7/9 implementation course details the operation of this core.
- The following courses could be of interest:
- USB Full Speed High Speed and USB On-The-Go, reference IP2 - USB 2.0 course
- CAN bus, reference IA1 - CAN bus course
- Theoretical course
- PDF course material (in English) supplemented by a printed version for face-to-face courses.
- Online courses are dispensed using the Teams video-conferencing system.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- ARM core based architecture
- APB internal busses
- The main three blocks : platform, core and input / output peripherals
- Presentation of the core, architecture and programming model
- Operating modes : user, system, super, IRQ, FIQ, undef and abort
- Pipeline
- ALU data path
- ARM vs Thumb instruction sets, interworking
- Access to memory-mapped locations, addressing modes
- Stack management
- Branch instructions, implementation of C call and return statements
- Benefits of condition set capability in ARM state
- C-to-Assembly interface
- Exception mechanism, handler table
- Debug facilities
- APB Bridges, individual peripheral reset control, individual peripheral clock control
- Memory organization, linear 4 GB mapping
- Internal 16 kB SRAM
- Flash memory, bank and sector mapping, burst mode
- Program and erase sequences
- Interrupt controller
- ISR header and footer routines
- External interrupts Unit
- System timers : Real Time Clock, Watchdog timer
- Power supplies, external 3.3V, internal generation of 1.8V, related pins
- Low voltage detectors
- Clocking
- Reset causes
- Start-up sequence, fetch of the first instruction
- Boot configuration register
- Low power modes
- External Memory Interface
- Description of the programming interface related to the 4 external chip-selects
- DMA
- Circular Buffer Management
- Support for UART, SPI / SSI, Timers and ADC
- Timers
- 16-bit timers, block diagram, clock selection and prescalers
- Output compare and input capture capabilities, force compare modes
- Output PWM mode, on-the-fly modification of the duty cycle
- Input PWM mode, pulse measurement
- Analog-to-Digital Converter
- High impedance-analog input configuration
- ADC features : 10-bit resolution, 0 to 2.5 V range
- Round-robin or single channel mode
- Clock timing
- The Sinc decimation filter
- Gain and offset errors
- I2C interface
- I2C protocol basics
- Slave mode vs master mode
- Transmit and receive sequences
- SPI / SSI
- SPI protocol basics
- Queue mode operation
- Transfer sequence
- UART
- Queue operation mode
- Time-out mechanism
- LIN capability
- SmartCard asynchronous protocol
- CAN controller
- CAN protocol basics
- CAN controller organization
- Message objects
- Filtering received messages
- FIFO mode management
- Configuring the bit timing
- USB slave interface
- USB protocol basics
- Buffer description block, buffer descriptor table
- Double buffer usage to support isochronous and high throughput bulk transfers
- Endpoint initialization