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Multicore implementation

This course tackles multicore implementation issues

Objectives

  • This course describes the multiple types of multicore implementations : SMP, AMP.
  • It details the hardware resources required to support SMP.
  • Debug issues are also studied.

  • ACSYS offers a large set of multicore processor trainings: ARM Cortex-A9MP (reference R6), NXP MPC8641D (reference FC5) and MPC8572E (reference FN10).
A more detailed course description is available on request at training@ac6-training.com
  • Knowledge of high-end processor cores is recommended.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • AMP
  • SMP
  • BMP
  • Applications examples (MPC8641D, MPC8572, Virtex-4, Virtex 5)
  • Exclusive resource management
  • MMU page descriptor table, PowerPC tlbsync instruction
  • Multi-core interrupt controller
  • Inter-Processor Interrupts
  • Message passing
  • System booting
  • Defining shared resources and non-shared resources
  • Assigning a number to each core
  • Dispatching tasks to a particular core, static approach, dynamic approach
  • I/O management, consequence on driver design
  • Software coherency (Power instructions dcbz, dcbf, dcbi, icbi)
  • Hardware coherency : snooping
  • Distinguishing two types of cache enabled area : random access vs sequential access, NUMA model
  • PLB basics
  • Exclusive resource management, lwarx/stwcx.
  • Implementing a multi-core interrupt controller
  • Synchronizing time bases
  • Is SMP possible in a multi-405 FPGA ?
Duration
2 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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