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V3 Design with SystemC

System Design and Simulation with SystemC

Objectives
  • Understand the benefits of system simulation with SystemC
  • Mastering the different levels of modeling
    • Transactional Models
    • Software models
    • Hardware models
    • Synthesizable models
  • System modeling:
    • UTF (UnTimed Functional model)
    • TF (Timed Functional model)
  • Hardware modeling:
    • BCA (Bus Cycle Accurate model)
    • PCA (Pin Cycle Accurate model)
This course is complemented by numerous exercises and describes SystemC version 2.2
  • Theoretical course
    • PDF course material (in English) supplemented by a printed version for face-to-face courses.
    • Online courses are dispensed using the Teams video-conferencing system.
    • The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
  • At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
  • Basic knowledge of C++ (see for example our L3 - C++ course)
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • Object Oriented Programming
    • Classes and objects
    • Attributes
  • Methods and operators
    • Overloading
    • Constructors and Destructors
    • Virtual methods
    • References
    • Default parameters
  • Memory management
    • The new and delete operators
  • Name spaces
  • Standard input/output (Streams)
  • Class and function templates
    • Template definition
    • Constraints
    • Automatic instantiation
    • Manual instantiation
  • Type conversions
    • Implicit conversions
    • User-defined conversions
    • Copy and initailisation operators
    • Up casts and down casts
  • Exceptions
  • The basics of SystemC
    • Language objectives
    • History
    • Advantages and disadvantages of SystemC
  • Transaction Level Modeling (TLM)
  • The SystemC design flow
    • Algorithmic model
    • TLM model
    • Hardware/software partitioning
    • Direct synthesis or HDL translation
    • Model simulation
  • The SystemC architecture
    • Communication channels
    • Structural elements
    • Data types
    • The simulation engine
  • Structural elements
    • Modules, Ports and Signals
    • Primitive Channels
  • Creating model structure
    • Instantiating Modules
    • Connecting ports
  • Processes and Time Management
    • Methods and Threads
    • Events
    • Static or dynamic sensitivity
    • Time and clocks
    • Dynamic processes
  • Starting and stopping the simulation
  • Model elaboration
    • Static elaboration phases
    • Dynamic elaboration phases
    • The event finder concept
    • Elaboration callbacks
  • The simulation phases
    • Event notifications
    • Waiting on events and triggers
    • Event queues
  • Debug techniques
    • Reporting and tracing
    • Error handling
    • Tracing hidden signals and local variables
  • Modeling busses
    • Interfaces and communication channels
    • Master and slave interfaces
    • Interface methods (blocking and non-blocking)
    • Using events with channels
    • Channels with dynamic sensitivity
  • Modeling multi-port busses
    • Port binding policies
  • Pin Accurate Models
    • Fully specified data types
    • Assignment and truncation
  • Logical types and vectors
    • Selecting bits and slices
    • Concatenating values
    • Resolving types
  • Integer and fixed point types
  • Refining algorithms
    • Creating UnTimed Functional (UTF) models
    • Refining to Timed Functional (TF) models
    • Partitioning hardware and software
    • Adding timing annotations
  • Refinement policies
    • Refining structure
    • Refining data
    • Refining communications
  • Channel refinement
    • The adaptator concept
    • Building an adaptator
    • Creating a specialized event finder
Duration
4 days
Cost
2490 € HT
Calendar
Session calendar
Inquire

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).

Last update of course schedule: 10 January 2022

Booking one of our trainings is subject to our General Terms of Sales

See also our other FPGA trainings