PDF course material (in English) supplemented by a printed version for face-to-face courses.
Online courses are dispensed using the Teams video-conferencing system.
The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
Any embedded systems engineer or technician with the above prerequisites.
The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
6-bus architecture, organization of a board based on MV64660
Frequency domains, fast path between CPU and SRAM / SDRAM
Data integrity checking
Internal crossbar
Master de-mux programming, address decode windows
Slave mux programming, pizza arbiters operation
CPU address space decoding
CPU-to-PCI address remapping
Protection windows
Arbitration, multi-processor operation
CPU slave operation
Cache coherency
Deadlock avoidance
Transaction ordering
Hardware implementation, clocking, low power modes
Introduction to DDR SDRAM from Jedec specification
DDR2 on-die terminations
Clocking
Initialization sequence
Data synchronization : DQS signals, programmable DLL
DDR2 SDRAM controller, functional description
Page management
Read and write transactions
ECC and read-modify-write transactions
Hardware implementation, ODT management (internal and external)
Low power modes
Transaction queue, read and write data buffers
Address and data multiplexing
Timing parameters
External acknowledgement
Pack / unpack and burst support
NAND flash support, boot from NAND flash
PCI bus arbitration
Master operation in PCI and PCI-X mode
Target operation in PCI and PCI-X mode
PCI-to-PCI configuration transactions
Address decoding
Integrated low power SERDES PHY
x1, x4 link
Operating as either Root Complex or Endpoint
Link initialization
Arbitration and ordering
Peer-to-peer traffic
Messaging unit, synchronization between CPUs through PCI/PCI-Express
GPIO port, functional description
Interrupt request inputs
Multi Purpose Pin multiplexing
Watchdog timer
Interrupt controller functional description
Interrupt steering logic to 4 possible output pins
Priority mechanism
Master and slave operation, 7- or 10-bit addressing
Determining the current state of the controller by reading the status register
Master write sequence, master read sequence
Slave write sequence, slave read sequence
Reset pins and configuration
Utilization of the boot sequencer
Requirement for an external Central Resource CPLD
IDMA address decoding
Target unit and attributes programming
Functional description, external control
Normal mode vs chained mode
Transfer descriptors, descriptor ownership
Channel activation
DMA interrupts
State machine : Active, Inactive and Paused states
XOR, CRC and DMA operation modes, format of transfer descriptors
XOR operation mode
CRC32 operation mode
DMA operation mode
Memory Initialization operation mode
ECC error cleanup operation mode
Arbitration between XOR engine0 and XOR engine1
Address override capability
XOR Engines interrupts
FIFO mode
Flow control
Transmit sequence
Receive sequence
Address decoding
Integrated PHY
USB host operation, EHCI specification support
USB device operation, Endpoint configuration
Dedicated DMA for data movement between memory and port
Integrated PHY, 3.0 or 1.5 Gbps bit rate
EDMA request and response queues
Studying the sequence that the software must implement to perform a PIO transfer
Studying the sequence that the software must implement to perform a DMA transfer
Queued DMA
Interrupt coalescing
Port multiplier support
SGMII support
Dedicated DMA
Related interrupts
Transmit weighted round-robin arbitration
Backpressure mode
Transmit and receive sequences
Management interface
MIB
Cryptographic engine functional description
Involved units : CPU, dedicated SRAM and security accelerator
Authentication
Encryption and decryption, supported algorithms
TDMA controller, attaching TDMA to security accelerator