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II1 DigRF and RFFE

This course covers DigRF and RFFE MIPI buses

formateur
Objectives
  • The course starts with an overview of MIPI specification.
  • Chapters are studied with a bottom-top approach, starting with M-PHY and ending with RFFE.
  • DigRF protocol, particularly frame acknowledgment, is detailed.
  • The course describes the DigRF startup sequence.
  • Connection to the antenna via RFFE is explained, focusing on both physical layer and protocol.
  • Test modes are also covered.
  • Companies interested in attending this course must adhere to MIPI organization.
  • This course has been designed for engineers in charge of SoC architecture, functional verification or silicon validation.

A more detailed course description is available on request at training@ac6-training.com
Prerequisites
  • Basic knowledge on digital electronics.

INTRODUCTION TO MIPI SPECIFICATIONS
M-PHY
  • Termination scheme
  • Signaling schemes
  • M-PHY type II modules
  • Embedding clock into the bitstream, 8b10b coding
  • DC-balancing, running disparity
  • PHY state definition
  • HS-MODE BURST Operation
  • SYS-BURST operation
  • Configuration attributes
  • Test modes
  • Electrical characteristics, eye-diagrams
  • Jitter influence on LINE characterization
  • Recommended test functionality
DIGRF INTERFACE
  • Overview
  • Physical layer based on M-PHY Type-II
  • 8b/10b control character mapping
  • Interface states
  • Protocol
  • Programming model
DEVICE DESCRIPTOR BLOCK (DDB)
  • Services to transfer descriptor and configuration data between devices on a MIPI Interconnect
  • Underlying interconnect requirements
  • DDB-PDU format
  • DDB protocol support for Level 1 and Level 2 services
RF FRONT-END CONTROL INTERFACE (RFFE)
  • Two-wire, serial interface
  • Point-to-multipoint connectivity
  • Time-accurate triggering mechanisms
  • MIMO configuration
  • Operating states
  • Physical layer
  • Protocol layer
  • Command sequences
  • Broadcast messages
  • Device enumeration, device identification