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IA2 FlexRay 2.1

This course covers the FlexRay specification version 2.1

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Objectives
  • The course details the hardware implementation and describes the tests required to check the compliance of an equipment.
  • The communication scheme which enables both Time and event-triggered communications is explained.
  • The course focuses on error recovery mechanisms.
  • Implementation examples are described through NXP and Philips existing devices.
A Lecroy analyser is used to capture and display FlexRay traffic.
•  A lot of traces are included in the material.
A more detailed course description is available on request at training@ac6-training.com
  • Experience of a digital bus is mandatory.
  • Theoretical course
    • PDF course material (in English) supplemented by a printed version for face-to-face courses.
    • Online courses are dispensed using the Teams video-conferencing system.
    • The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
  • At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • History, X-by-Wire
  • Possible topologies
  • Deterministic data transmission
  • Partitioning
  • Security mechanisms
  • Time and event-triggered communications
  • Synchronized time-bases on macrotick basis
  • Time division, slot duration and slot number configuration
  • FTDMA dynamic part of a communication cycle
  • Mini-slot allocation
  • Frame format
  • Message oriented addressing via identifiers
  • Symbol transmission
  • Bus controller
  • SPI interface
  • CPU parallel interface
  • Node wake-up, power saving mode
  • Media Access Control
  • Fault-tolerant and time-triggered services
  • Repetitive vs spontaneous message scheduling
  • Dedicated online diagnosis services
  • Redundant transmission channels
  • Robust coding and bit recognition scheme
  • Error detection and signaling
  • Fault confinement in the Time Domain, Bus Guardian
  • Signal level and bit representation
  • Transmission medium
  • Fault confinement
  • Error detection and signalling
  • Message validation
  • Message framing
  • Scheduling and access control
  • Status signalling
  • Frame and data handling
  • Frame filtering and masking
  • Stopping communication
  • Loss of synchronization
  • Degradation concept
  • Immediate passivation
  • Error signalling
  • Compliance checklists
  • Physical layer testing
  • Protocol conformance verification