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ARM fundamentals

This course covers ARM architecture V4T and V5TE fundamentals

Objectives

  • ARM modes state machine is detailed, clarifying the register banking mechanism.
  • Subtelties of ARM instruction set are covered, such as conditional execution, addressing modes, operand shifting.
  • Interworking between ARM and Thumb instruction sets is explained.
  • The exception mechanism is studied, particularly interrupt nesting.
  • The course also covers ARM926EJ-S cache and MMU operation.
Labs are run under RVDS
A more detailed course description is available on request at training@ac6-training.com
  • Basic knowledge of CPU or DSP.
  • This one-day course has been designed to meet the pre-requisites of ARM11 and Cortex-A/R courses.
    This is a summary of ARM7/9 course.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • ARM operation modes
  • The ARM registers set, register organization summary according to the current mode
  • Program Status Registers
  • Exception handling, vector table, automatic switch into ARM mode
  • Conditional execution and flags
  • Branch instructions
  • The barrel shifter
  • Immediate constants
  • Single register data transfer
  • Stack management
  • Register access in Thumb
  • ARM architecture V5TE new instructions
  • Switching between states
  • Mixing ARM and Thumb subroutines
  • ARM to thumb veneer
  • Thumb-to-ARM veneer
  • Interworking calls
  • Exception priority
  • Vector table instructions
  • Chaining exception handlers
  • FIQ vs IRQ
  • Example C interrupt handler
  • Issues when reenabling interrupts
  • C nested interrupt example
  • Data abort with memory management
  • Adjusting the return address
  • Introduction to page management
  • Translation Lookaside Buffer
  • Benefits of Fast Context Switch Extension
  • ARM926 MMU
  • Organization of page descriptor tables
  • Configuration & control through CP15
  • Cache basics
  • Hit under miss and its consequence: out of order abort
  • Highlighting data flows between main memory and caches
  • Write buffer
  • Tightly coupled memories
Duration
1 day
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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